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ISO-CMOS ST-BUSTM FAMILY MT8926 T1 Performance Monitoring Adjunct Circuit (PMAC)
Features
* * * * * * * * ANSI T1.403 and T1.408 Performance Monitoring and Maintenance Functions Operates in conjunction with Mitel's T1/ESF framer circuits (MT8976/77 and MH89760B) D3/D4 (SF), and ESF modes of operation One and two second timers Supports bit-oriented and message-oriented data transfer over the Facility Data Link (FDL) ESF and D3/D4 Yellow Alarms, Alarm Indication Signal and Loss of Signal Indication Framing Error, CRC Error and Bipolar Violation Error counters Alarm interrupts and counter overflow interrupts
ISSUE 3
July 1993
Ordering Information MT8926AE MT8926AP 28 Pin Plastic DIP 28 Pin PLCC
-40C to 85C
Description
The MT8926 Performance Monitoring Adjunct Circuit (PMAC) interworks with Mitel's MT8976/77 and MH89760B to provide performance monitoring data, alarms and T1 maintenance features. It meets the performance monitoring and maintenance requirements of ANSI T1.403 and T1.408, and also supports Channel Service Unit (CSU) requirements.
Applications
* * * T1 line performance data collection CSU performance monitoring ISDN Primary Rate maintenance controller
FDLi E8Ki Transmit BOM Register Receive BOM Register & RAI Debounce IRQ C2i CSTi0 CSTi1 CSTo BSI RESET ST-BUS Interface SnapShot Registers FSI SEI 4 Bit SE Counter 4 Bit FE Counter
E8Ko E8K/FDL Mux FDLo
FDL Extractor Framer, SE/FE Detector Line Loopback Integrator
VDD
VSS
8 Bit BPV Counter RxA B8ZS Recovery, BPV Detector RxB ECLK
DSTi0 DSTi1 DSTo F0i
Payload & Line Loopback Control
8 Bit CRC Counter CSI AIS/LOS Detector Timer 1SEC
Figure 1 - Functional Block Diagram
4-3
MT8926
28 PIN PLASTIC DIP
28 PIN PLASTIC J-LEAD
Figure 2 - Pin Connections
Pin Description
Pin # 1 2 Name VSS ECLK System Ground. Extracted Clock Input. A 1.544 MHz clock derived from the received data. This signal is used to clock in the data on pins RxA and RxB. See Figure 11 for timing information. Receive A Input. A unipolar active low signal decoded from the received T1 signal. See Figure 11 for timing information. Receive B Input. A unipolar active low signal decoded from the received T1 signal. See Figure 11 for timing information. Internal Connection. Must be tied to VSS for normal operation. Extracted 8 kHz Input. A low going pulse on this input is used by the PMAC to locate the framing bit in the received signal. The device uses this information to detect errors in the received framing bits. Connect to E8Ko of the MT8976/77. See Figure 12 for timing information. 8 kHz clock output. The 8 kHz signal input at E8Ki is output on this pin when bit 2 (8KEn) of the PMAC Control Word is set. The output is pulled high when 8KEn is reset. See Figure 12 for timing information. System Ground. Control ST-BUS Output. The data that enters the PMAC on CSTi0 will exit the device on this pin. Data derived by the PMAC will be inserted into specific channels of this output stream. See Figures 13 and 14 for timing information and Figure 5 for channel allocation. Control ST-BUS Input 0. Accepts the serial ST-BUS stream output on CSTo of the MT8976/77. The data that enters the PMAC on this pin exits the device on CSTo. The contents of specific CSTi0 channels is replaced by data derived by the PMAC. See Figures 13 and 14 for timing information and Figure 4 for channel allocation. Control ST-BUS Input 1. Channel 11 of this ST-BUS input stream is used to control specific features in the device (Table 14). Channel 7 is used for the transmit bit-oriented message (Table 13), and channel 15 is used to control loopback functions (Table 4). See Figure 13 for timing information and Figure 3 for channel allocation. Frame Pulse Input. This input accepts an 8 kHz signal, which is used to delineate the STBUS frame boundary. See Figure 15 for timing information. Description
3 4 5 6
RxA RxB IC E8Ki
7
E8Ko
8 9
VSS CSTo
10
CSTi0
11
CSTi1
12
F0i
4-4
F0i C2i VSS VDD RESET FLDi FLDo
VSS ECLK RxA RxB IC E8Ki E8Ko VSS CSTo CSTi0 CSTi1 F0i C2i VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDD IC DSTi1 DSTi0 DSTo IC VSS IC IRQ 1SEC FDLo FLDi RESET VDD
IC E8Ki E8Ko VSS CSTo CSTi0 CSTi1
4 3 2 1 28 27 26 25 5 24 6 23 7 22 8 21 9 20 10 19 11 12 13 14 15 16 17 18
ECLK VSS VDD IC DSTi1 DSTi0 DSTo IC VSS IC IRQ 1SEC
RxB RxA
MT8926
Pin Description (Continued)
Pin # 13 Name C2i Description 2.048 MHz Clock Input. This input accepts a 2.048 MHz clock signal, which is used to clock ST-BUS control and data streams into and out of the PMAC. See Figures 13 and 14 for timing information. System Ground. Supply Voltage Input (+5 V). RESET Input. Must be high for normal operation. MT8926 will be suspended. When low, the functions of the
14 15 16 17
VSS VDD RESET FDLi
Facility Data Link Input. This input accepts a 4 kbit/sec. facility data link transmit signal, which is routed back out transparently on FDLo if message-oriented signal transmission is enabled (i.e., PMAC Control Word bit 0, FDLEn, is low). This signal is not clocked into the PMAC. If bit-oriented messaging is enabled (FDLEn high), data on this input will not be routed to FDLo (see pin 18, FDLo, below). Facility Data Link Output. When bit-oriented messaging is enabled (i.e., PMAC Control Word bit 0, FDLEn, is high), data in the Transmit BOM register will be appended to a 1111 1111 (FF) flag and clocked out of the device at this output. The output timing for this signal is shown in Figure 18. When bit-oriented messaging is disabled (FDLEn low), data received at the FDLi pin is routed back out transparently on this pin (it is not re-timed). See Figure 19 for timing information. 1 Second Output. A one second timing signal derived from the ST-BUS F0i signal is output on this pin. The output is low for 0.5 seconds and high for 0.5 seconds. It can be used as an interrupt source to generate T1.403 message-oriented performance reports. See Figure 16 for timing information. Interrupt Request Output. An open drain output that is to be externally connected to VDD through a pull-up resistor. The PMAC will pull this pin low to assert an interrupt request. Interrupting events and their groupings are described in Tables 16 and 17. IRQ is released by making bit 1 (Interrupt Acknowledge - INTA) of the PMAC Control Word low. Once INTA is set, all interrupting signals of a particular group must be inactive before the next interrupt of that group can assert IRQ. See Figure 17 for functional timing information. Internal Connection. Must be left open for normal operation. System Ground. Internal Connection. Must be left open for normal operation. Data ST-BUS Output. A 2.048 MBit/sec. serial output stream, which contains the 24 PCM or data channels to be transmitted on the T1 trunk. This data stream is multiplexed from either input DSTi0 (Normal Mode) or input DSTi1 (Payload Loopback Mode). The selection of either the Normal or Payload Loopback mode is made through the Loopback Control Word. This output should be connected to DSTi of the MT8976/ 77. When the loopback control word is set for line loopback code generation, the 24 PCM channels will contain the line loopback activate or deactivate code stream. See Figure 14 for timing information. Data ST-BUS Input 0. A 2.048 MBit/sec. serial input stream, which contains the 24 PCM or data channels to be transmitted on the T1 trunk in Normal Mode. This input should be connected to the system side output stream. Data ST-BUS Input 1. A 2.048 MBit/sec. serial input stream, which contains the 24 PCM or data channels to be transmitted on the T1 trunk in Payload Loopback Mode. This input should be connected to DSTo of the MT8976/77. Internal Connection. Must be tied to V SS for normal operation. Supply Voltage Input (+5 V).
18
FDLo
19
1SEC
20
IRQ
21 22 23 24
IC VSS IC DSTo
25
DSTi0
26
DSTi1
27 28
IC VDD
4-5
MT8926
Functional Description
The MT8926 Performance Monitoring Adjunct Circuit (PMAC) is designed to enable a MT8976/77 based T1 interface to gather performance data and perform maintenance functions as per ANSI T1.403 and T1.408. Performance data collection includes CRC errors, severely errored framing events, frame synchronization-bit errors, line code violations, and controlled slips. Maintenance functions include the detection of alarms, SF line loopback code generation and detection, ESF payload loopback, as well as the transport of bit-oriented and messageoriented signals over the Facility Data Link (FDL). The control and status data of the MT8926 is transported over spare channels of the existing MT8976/77 ST-BUS streams. Therefore, no new STBUS streams are required to upgrade with the PMAC. The PMAC has an on-board framer that uses the received signal and extracted 8 kHz clock to achieve synchronization. The result of this frame alignment is logically ANDed with the SYN bit of the MT8976/77 CSTo stream to give FECV (see Table 5). This will ensure that the PMAC can only declare synchronization after the framer is synchronized. The MT8926 will align to SF or ESF framing without user selection. An interrupt (IRQ output) system is also provided to reduce the requirement to monitor ST-BUS channels continuously for exception conditions. Interrupt sources are divided into group one (G1) for service affecting events and group two (G2) for counter overflows. A timer has been included to allow scheduling of T1.403/408 message-oriented performance reports for transmission over the facility data link. This timer
0-2 CSTi1 PCCW 2 T1 1-3 3 X 4-6 7 8-10 PCCW Tx PCCW 2 BOM 2 4-6 7-9 11 PC W 12-14 PCCW 2 10-12
provides a two second output (register accessed) and a one second output pin. Two eight bit counters with overflow bits and resets (resets counter and overflow bit) are provided to record line code violations (BPV) and CRC errors. The BPV counter will not count B8ZS encoding violations. When either overflow bit goes high it will generate a group two (G2) interrupt. Two four bit counters are used to record framing error events (FE) and severely errored framing events (SE). The FE counter has an overflow indication bit and can be cleared (resets counter and overflow bit) by the user. Its overflow bit will generate a group two (G2) interrupt when it goes high. A G2 interrupt will also be issued whenever the SE counter is incremented. The alarms that the PMAC monitors are alternate SF yellow alarm (i.e., twelfth SF framing bit =1, ALRM), ESF facility data link yellow alarm (RAI), loss of signal (i.e., reception of 128 or more consecutive zeros), and alarm indication signal (AIS, blue alarm or all ones alarm). Therefore, the MT8926/MT8976/ 77 combination supports a comprehensive alarm package. The PMAC alarm registers and counters are updated as the corresponding events occur. Once per frame (8000 times a second) the state of these registers and counters is recorded in a set of snap-shot registers. This data in the snap-shot registers is then inserted into the appropriate bit positions of the STBUS status stream CSTo. FDL bit-oriented messages can be communicated via the PMAC transmit and receive bit-oriented message registers. The user gains access to these registers through the ST-BUS control streams. Valid bit-oriented messages consist of a series of
15 LC W 16-18 PCCW 2 13-15 19 20-22 X PCCW 2 16-18 23 X 24-26 PCCW 2 19-21 27 28-30 31 X PCCW X 2 22-24
PMAC Control Word Transmit Bit-Oriented Message Register Bit 7 0 Function Transmitted First Transmitted Last Bit 7 6 5 4 3 2 1 0 Function SER FER CRCR BPVR FSel 8KEn INTA FDLEn Loopback Control Word Bit 1 0 0 1 1 Bit 0 0 1 0 1 Function Normal Payload Loopback Line Loopback Enable Code (00001) Line Loopback Disable Code (001)
PCCW = Per Channel Control Word
FIgure 3 - CSTi1 Channel Allocation Versus T1 Channels
4-6
MT8926
repeating 16 bit code words of the form: 11111111 0XXXXXX0, where XXXXXX is the message content. The PMAC will automatically append the prefix byte 11111111 to the transmit message and remove it from the receive message. It will also indicate the reception of a valid message. When bit-oriented messages are not being transported, messageoriented facility data link signals, assembled by an external HDLC controller (i.e., MT8952), can be passed through the PMAC to the MT8976/77 for transmission. The PMAC can implement an ESF payload loopback by routing the MT8976/77 DSTo stream to the MT8976/77 DSTi input (see Figure 6). The payload loopback is controlled through the loopback control word, Channel 15 of CSTi1 (see Figure 3). When the payload loopback is disabled, data entering the PMAC's DSTi0 pin is transferred to the PMAC DSTo. DSTo of the PMAC should be connected to the DSTi pin of the MT8976/77 framer. PMAC - Framer Interworking The MT8926 PMAC is designed to function with the MT8976/77 T1 framer. Figure 9 illustrates a typical application and the connections involved in realizing this interface. Both the PMAC and framer receive the extracted clock and data from the T1 line interface. This allows the MT8926 to perform B8ZS recovery and BPV detection, as well as SF or ESF synchronization, framing error detection, facility data link extraction, and line loopback code detection. Some of the CSTi1 channels that are not used to control the MT8976/77 are used to control the PMAC, therefore, CSTi1 will connect to both devices. Figure 3 shows the channels of CSTi1 that carry the MT8976/77 Per Channel Control Words, as well as the MT8926 control data. C2i and F0i supply timing references for both devices. The CSTo stream of the MT8976/77 framer enters the PMAC on CSTi0 (see Figure 4). The PMAC adds its performance data to form the CSTo stream of the PMAC. Figure 5 shows the channels and status bits that the PMAC has added to CSTo. E8Ko of the framer will also pass through the PMAC, E8Ki to E8Ko, under control of CSTi1. It should be noted that the PMAC will replace some of the data of MT8976/77 Master Status Words 1 and 2. This is outlined in Tables 1 and 2. Bit
7 6 5 4 3 2 1 0
MT8976/77 CSTo
YLALR MIMIC ERR ESFYLW MFSYNC BPV SLIP SYN
MT8926 CSTo
YLALR MIMIC ALRM RAI MFSYNC LOS SLIP SYN
Table1. Master Status Word 1 Data Substitution Bit
7 6 5 4 3 2 1 0
MT8976/77 CSTo
BlAlm FrCnt Xst BPVCnt BPVCnt CRCCNT CRCCNT CRCCNT
MT8926 CSTo
BlAlm FrCnt Xst SEI FSI CSI BSI AIS
Table 2. Master Status Word 2 Data Substitution The MT8926 can be programmed to either pass data through from FDLi to FDLo and on to the MT8976/77 input TxFDL, or insert bit-oriented messages into the FDL via the transmit bit-oriented message register, channel 7 of CSTi1. This function is under control of the FDLEn bit of the PMAC Control Word. See Application section Figure 9 for FDL connections. Channel 15 of CSTi1, the Loopback Control Word, is used to control the line loopback code generation and payload loopback functions of the PMAC. This is done by internally connecting the MT8926 DSTo to either a line loopback enable code generator, a line loopback disable code generator, DSTi0 or DSTi1. Figure 6 illustrates the connections required to support these functions. The DSTo of the framer
15 MS W1 16-18 PCWS 19 X 20-22 PCSW 23 X 24-26 PCSW 27 X 24-26 PCSW 31 MS W2
CSTi0 0-2 MT8976/77 PCSW CSTo T1 PCSW PSW MSW = = = 1-3
3 4-6 PS PCSW W 4-6
7 X
8-10 PCSW
11 X
12-14 PCSW
7-9
10-12
13-15
16-18
19-21
22-24
Per Channel Status Word Phase Status Word Master Status Word
FIgure 4 - MT8926 CSTi0 (MT8976/77 CSTo) Channel Allocation Versus T1 Channels
4-7
MT8926
CSTo
0-2 3 4-6 PCSW PS PCSW W 1-3 4-6
7 PM SW
8-10 11 12-14 PCSW CRC PCSW
15 MS W1
16-18 PCSW
19 20-22 23 24-26 27 28-30 31 EF PCSW BPV PCSW Rx PCSW MS EC 2 BOM W2 16-18 19-21 22-24
T1
7-9
10-12
13-15
PMAC Miscellaneous Status Word Bit 7-5 4 3 2 1 0 Function Not Used LLDD (001) LLED (00001) FECV TMR (2SEC) BOMV
Cyclic Redundancy Check-6 Error Counter Bit 7 0 Function MSB LSB Master Status Word 1 Bit 7* 6* 5 4 3* 2 1* 0* Function YLALR MIMIC ALRM RAI (ESF YELLOW) MFSYNC LOS SLIP SYN Bit 7-4 3-0
Errored Frame Event Counter Function SE (MSB-LSB) FE (MSB-LSB)
Received Bit-Oriented Message Register Bit 7 0 Function Received First Received Last Master Status Word 2 Bit 7* 6* 5* 4 3 2 1 0 Function BlAlm FrCnt Xst SEI FSI CSI BSI AIS
Bipolar Violation Counter Bit 7 0 Function MSB LSB
PCSW = Per Channel Status Word PSW = Phase Status Word * MT8976/77 Data unaltered by the MT8926
Figure 5 - CSTo Channel Allocation Versus T1 Channels connects to DSTi1 of the PMAC and to the receive side of the system. This allows the PMAC to perform a payload loopback by internally connecting DSTi1 to DSTo. In normal operation, transmit data will flow from DSTi0 to DSTo of the PMAC to DSTi of the MT8976/77. PMAC RESET The MT8926 functions may be suspended by making the RESET input low (RESET must be high for normal operation). In the reset state, data entering the PMAC on FDLi, DSTi0 and CSTi0 will pass through unaltered to FDLo, DSTo and CSTo respectively. E8Ko will be high, IRQ will be high impedance and the 1SEC output (and TMR bit) will be low. After the MT8976/77 has acquired frame synchronization and RESET returns high, the MT8926 will require two superframes to acquire synchronization and two ST-BUS frames to align to the ST-BUS. RESET can be used to prevent DS1 interface
RxA RxB ECLK To PMAC Control 4 to 1 MUX CSTi1 Repeating 00001 DSTo ST-BUS Transmit Data Stream ST-BUS Receive Data Stream DSTi0 DSTi1 DSTi TxA CSTi1 From System Control MT8976/77
MT8926
Repeating 001
DSTo
TxB
LCW LCW 00 01 10 11 Function DSTi0 to DSTo DSTi1 to DSTo 00001 to DSTo (activate) 001 to DSTo (deactivate)
LCW = Loopback Control Word
Figure 6 - Payload and Line Loopback Operation
4-8
MT8926
Bit 7-6 Name YLALR & MIMIC ALRM Description These bits (Yellow Alarm Indication and Mimic) contain information from the MT8976/77 that is unaltered by the MT8926. See Master Status Word 1 of the MT8976/77 data sheet. Alarm. This bit will be set if the MT8926 detects a 1 in the FS bit position of the twelfth frame of an SF superframe (alternate yellow alarm indication). ALRM will be low when the FS bit is 0. When receiving an ESF signal or if bit 3 (FSEL) of the PMAC Control Word (CSTi1 Channel 11) is low, the ALRM bit will always be low. Remote Alarm Indication (also known as ESF Yellow Alarm). This bit is set if an RAI code word (repeating hex FF00 pattern) is received on the ESF facility data link. This code must be correctly detected in seven out of 10 messages. RAI will be reset if more than three of 10 messages are in error. When receiving an SF signal, this bit will always be low. This bit (Multiframe Synchronization) contains information from the MT8976 that is unaltered by the MT8926. See Master Status Word 1 of the MT8976 data sheet. Loss of Signal. This bit will go high when the MT8926 detects 128 or more consecutive zeros in the line signal. It will be reset after the device detects a 12.5% ones density (48 ones in two or less frames) in the received signal. These bits (Slip Indication and Synchronization) contain information from the MT8976/77 that is unaltered by the MT8926. See Master Status Word 1 of the MT8976/77 data sheet. Table 3. Master Status Word 1 (CSTo Channel 15)
5
4
RAI
3 2
MFSYNC LOS
1-0
SLIP & SYN
Bit 1 0 0 1
Bit 0 0 1 0
Description Normal operation. The transmit data applied to DSTi0 will pass through the PMAC, and be output on DSTo. Payload Loopback mode. Connect as per Figure 6. The received data on DSTo of the MT8976/77 is routed through the PMAC to the DSTi input of the MT8976/77. Transmit Line Loopback Enable. Connect as per Figure 6. DSTo of the PMAC will be internally connected to an SF line loopback enable code generator. That is, a repeating 00001 code is placed in the 24 T1 channels of DSTo, so it may be transmitted by the framer. Transmit Line Loopback Disable. Connect as per Figure 6. DSTo of the PMAC will be internally connected to an SF line loopback disable code generator. That is, a repeating 001 code is placed in the 24 T1 channels of DSTo, so it may be transmitted by the framer. Table 4 - Loopback Control Word (CSTi1 Channel 15)
1
1
Note: Bits 2 to 7 of the Loopback Control Word are not used.
interrupts from occurring during system initialization. It should be noted that when the MT8926 is acquiring synchronization the CRC and BPV counters may record errors. ALRM (SF Yellow Alarm)
an ESF signal is being received or when FSel is low, ALRM will always be low. A low to high transition of the ALRM bit will initiate a group one (G1) interrupt. Remote Alarm Indication (RAI)
The MT8926 will recognize the sixth FS bit of an SF superframe as an alternate Yellow Alarm indicator, if FSel of the PMAC Control Word is high. That is, when this FS bit is high/low, the ALRM bit of Master Status Word 1 will be high/low (see Table 3). When
The PMAC will decode the bit-oriented priority codeword 11111111 00000000 received on the FDL as a Remote Alarm Indication (RAI or Yellow Alarm) signal as per T1.403/408. See the section on
4-9
MT8926
MT8926 FDL message transfer. This 16 bit pattern must be detected in seven out of 10 codewords in order for the RAI bit of Master Status Word 1 (CSTo channel 15 bit 4) to go high (see Table 3). If more than three out of 10 codewords are in error, then RAI will remain low. A low to high transition of the RAI bit will initiate a group one (G1) interrupt. See the section on interrupts for the control of the RAI interrupt. Loss of Signal Indication (LOS) The LOS bit of Master Status Word 1, Table 3, will be high if the MT8926 receives 128 or more consecutive zeros from the T1 interface. LOS will return low when a ones density of 12.5% has been achieved (approximately 48 ones is received in two or less frames). Payload Loopback The payload of a T1 signal consists of the 192 data bits of each frame and excludes the framing bit (the first bit of 193). Therefore, a T1.403 or T1.408 ESF payload loopback extracts the payload of a receive T1 signal and transmits it back to the originator with new framing bits. This allows the transport of maintenance and performance data over the facility data link while the payload loopback is activated. The CRC-6 multiframe alignment remainder will not be looped around, but will function normally (i.e., calculated for each direction of transmission).
)
Bit 7-5 4
Name --LLDD Not Used.
Description
Line Loopback Disable Detect. This bit is set when a repeating 001 pattern (either framed or unframed) is detected in the received T1 signal for at least five frames. In order to comply with T1.403, the user's operating system will ensure that this code is present for at least five seconds before deactivating the SF line loopback (MT8976/77 Remote Loopback). The MT8926 will detect this repeating bit pattern even in the presence of a BER of 3 errors in 1000 bits.
3
LLED
Line Loopback Enable Detect. This bit is set when a repeating 00001 pattern (either framed or unframed) is detected in the received T1 signal for at least five frames. In order to comply with T1.403, the user's operating system will ensure that this code is present for at least five seconds before activating the SF line loopback (MT8976/77 Remote Loopback). The MT8926 will detect this repeating bit pattern even in the presence of a BER of 3 errors in 1000 bits.
2
FECV
Framing Error Count Validation. This bit is set when the MT8926 has synchronized to a framed T1 signal. The framing error count is frozen if this bit is not set. Synchronization (FECV=1) is reported when the MT8926 detects two consecutive superframes with correct framing bits, and bit 0 in CSTi0 channel 15 (SYN) is zero. When receiving an SF signal, both FS and FT bits are examined if bit 3 (FSel) in the PMAC Control word is set. In this case the sixth FS bit is not examined when checking for framing bits. If bit FSel is reset, then only FT bits are examined. Loss of synchronization (FECV=0) is reported when either two out of four errors have been detected in the received framing bit position (SF FT bits or ESF FPS bits) or if bit 0 in CSTi0 channel 15 (SYN) is set indicating the MT8976/77 has lost synchronization.
1 0
TMR BOMV
Two Second Timer. This bit changes state once per second. Bit-Oriented Message Validation. This bit will be set when a valid bit-oriented message is present in the receive BOM register (Table 12, CSTo, channel 27). It is reset when a valid message is not being received. A valid bit-oriented message has the form 111111110XXXXXX0, where XXXXXX contains the message information. Table 5. PMAC Miscellaneous Status Word (CSTo Channel 7)
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MT8926
The MT8926 PMAC can perform a payload loopback by muxing the data received on the MT8976/77's DSTo to DSTi of the MT8976/77. This is controlled by the MT8926 Loopback Control Word (CSTi1 channel 15, see Table 4). Figure 6 illustrates the MT8926 payload loopback connections. The ST-BUS transmit stream (normally connected to DSTi of the MT8976/77) will connect to DSTi0 of the MT8926. The DSTo stream of the MT8976/77 will connect to DSTi1 of the MT8926 and to the ST-BUS receive stream. DSTo of the MT8926 will connect to DSTi of the MT8976/77. Line Loopback Codes T1.403 defines SF mode line loopback activate and deactivate codes. These codes are either a framed or un-framed repeating bit sequence of 00001 for activation or 001 for deactivation. The standard goes on to say that these codes will persist for five seconds or more before the loopback action is taken. The MT8926 will generate line loopback activate and de-activate codes. These functions are controlled by the Loopback Control Word of CSTi1 channel 15 (see Table 4). The connections illustrated in Figure 6 must be implemented for this feature to function. The MT8926 will also detect both framed and unframed line loopback activate and de-activate codes even in the presence of a BER of 3 errors in 1000 bits. See the PMAC Miscellaneous Status Word, Table 5, CSTo channel 7 bit 3 Line Loopback Enable Detect (LLED) and bit 4 Line Loopback Disable Detect (LLDD). The line loopback of T1.403 is equivalent to the remote loopback function of the MT8976/77 (see MT8976/77 data sheet, Master Control Word 2). Therefore, the user will monitor the LLED and LLDD bits to ensure that they persist for a minimum of five seconds. Then the line loopback can be either activated or de-activated using the MT8976/77 Remote Loopback function. PMAC Synchronization The MT8926 has its own frame synchronization mechanism, which uses the received signal (RxA and RxB) and E8Ki to achieve SF and ESF frame and superframe alignment. Further, the PMAC monitors the SYN bit of the MT8976/77 (CSTo channel 15 bit 0) and will not declare synchronization until it is clear. When SYN is low and the MT8926 framer is properly aligned for two superframes, the PMAC will declare synchronization by making the Frame Error Count Validation bit (FECV) high. If this criteria is not met, FECV will be low. The PMAC will use the received FT and FS bits, FT bits only or FPS bits to acquire synchronization. The receive FT or FPS bits are used to determine the outof-synchronization state (see Table 5). Timer Outputs The PMAC has two timer outputs, 1SEC pin and CSTo TMR bit, which are derived from the 8 kHz STBUS frame pulse F0i. These signals have been implemented to provide the interface controller with a timing reference for the transmission of T1.403/408 message-oriented performance data over the FDL. See the Application section for an explanation of T1.403/408 FDL Message Transfer. The 1SEC output (pin 19) changes state once every half second, and therefore, has a period of one second. The relationship between the 1SEC output and the frame pulse F0i is shown in Figure 16. TMR is bit one of the PMAC Miscellaneous Status Word (CSTo channel 7, see Table 5). It changes state once per second on the rising edge of the 1SEC output, and thus, has a two second period. Therefore, TMR will change state 62 C2i clock cycles (or ST-BUS bit times) after the frame pulse that immediately precedes the rising edge of the 1SEC output. Framing Error Event Counters The MT8926 has two four bit counters, the Framing Error Counter (FE) and the Severely Errored Framing Event Counter (SE). The FE counter will be incremented each time a single framing error in the T1 signal is received. The SE counter will be incremented by the reception of a T1 framing pattern with an error rate that is greater than or equal to two out of six bits. See Table 8 for errored frame event counter details. Frame #
1 2 3 4 5 6 7 8 9 10 11 12
FT
1
FS
0
0 0 1 1 0 1 1 1 0 0
Table 6. D3/D4 or SF Frame Pattern Table 6 illustrates the Terminal Framing bits (FT) and Signalling Framing bits (FS) of the SF or D3/D4
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MT8926
s
Framing Select FSel=0 FSel=1
SF (FT)
SF (FS)
ESF (FPS) XXXXXX 001011
101010 XXXXXX 101010 00111X
Table 7. Framing Bits which Affect the SE and FE Counters framing pattern. Refer to Table 18 for the ESF framing pattern. Table 7 illustrates which framing bits are included in the framing error calculations in SF and ESF modes with the Framing Pattern Selection bit (FSel), CSTi1 channel 11 bit 3, high and low. Bits marked "1" or "0" are counted, bits marked "X" are excluded. When an SF signal is being received and FSel is low the counters are incremented by FT framing bit error events. FSel must be high for the extended superframe FPS bits or both SF FT and FS bits to be included. It should be noted that the twelfth SF framing bit (the sixth FS framing bit) is excluded because it can be used as an SF alternate yellow alarm. The ALRM bit of the Master Status Word 1 (CSTo channel 15 bit 5) will be high if the received alternate yellow alarm bit is high. The ALRM bit will always be low if FSel is low. The FE and SE counters will wrap around to 0000 after reaching a terminal count of 1111. When the FE Bit 7-4 Name SE
counter wraps around the Framing Error Saturation Indication bit (FSI) will be set, Table 11, and a G2 interrupt will be asserted. The Severely Errored Framing Event Indication bit (SEI), Table 11, will be set when the SE counter is incremented. This will also assert a G2 interrupt. These counters are frozen when the PMAC or MT8976/77 has lost synchronization (i.e., CSTo Channel 7 bit 2, FECV = 0). The SE and FE counters, as well as the SEI and FSI bits are cleared by a high-to-low transition of bit 7, SE Counter Reset (SER), and bit 6, FE Counter Reset (FER), of the PMAC Control Word channel 11 CSTi1. BPV and CRC-6 Error Counters The MT8926 has two eight bit counters, the Bipolar Violation Counter (BPV), Table 10, and the CRC-6 Framing Error Counter (CRC), Table 9. The BPV counter is incremented each time a non-B8ZS bipolar code violation is received on the T1 interface. The PMAC performs B8ZS recovery of the receive data before BPVs are detected. The CRC-6 Framing Error Counter is incremented when the least significant bit of the MT8976/77 CRC error counter is incremented. The BPV and CRC counters will wrap around to 00000000 after reaching a terminal count of Description
Severely Errored Framing Event. This four bit counter is incremented when the MT8926 detects two out of six framing bit errors. It will wrap around after reaching terminal count and can be reset by toggling bit 7 of the PMAC Control Word (Table 14, CSTi1 channel 11) from high to low. When receiving a SF T1 signal, both FS and FT bit errors are counted if bit 3 in the PMAC Control Word is set high. If this bit is set low, only errors in the FT bits will be counted. When both FS and FT bit errors are counted, FS bit 6 (in the twelfth frame in an SF superframe) is not examined for errors because it can be used to indicate a Yellow alarm.
3-0
FE
Framing Error Count. This four bit counter is incremented when a framing bit error is detected. When receiving a SF T1 signal, both FS and FT bit errors are counted if bit 3 in the PMAC Control Word is set high. If this bit is set low, only errors in the FT bits will be counted. When both FS and FT bit errors are counted, FS bit 6 (in the twelfth frame in an SF superframe) is not examined for errors because it can be used to indicate a Yellow alarm. The counter shall wrap around after reaching terminal count and can be reset by toggling bit 6 in the PMAC Control Word (Table 14, CSTi1 channel 11) from high to low.
Table 8. Framing Error and Severely Errored Framing Event Counters (CSTo Channel 19)
4-12
MT8926
Bit 7-0 Name CRC Description CRC Error Counter. This is an 8 bit counter, which is incremented when the LSB of the MT8976/77 CRC counter toggles. The CRC error counter will wrap around after reaching terminal count (i.e., 11111111 to 00000000). This will also set bit 2 (CSI) of master status word 2. CRC is reset when bit 5 in the PMAC Control Word is toggled from high to low. This counter is invalid when a SF mode T1 signal is being received. Table 9. CRC-6 Error Counter (CSTo Channel 11) Bit 7-0 Name BPV Description Bipolar Violation Counter. This is an 8 bit counter, which is incremented when a line code violation is detected by the MT8926. The counter will wrap around upon reaching terminal count (11111111 to 00000000). This will also set bit 1 (BSI) of master status word 2. BPV is reset when bit 4 in the PMAC Control Word is toggled from high to low. Table 10. Bipolar Violation Counter (CSTo Channel 23) Bit 7-5 Name BlAlm, FrCnt & Xst SEI Description These bits (Blue Alarm, Frame Count and External Status) contain information from the MT8976/77 that is unaltered by the MT8926. See Master Status Word 2 of the MT8976/77 data sheet. Severely Errored Framing Event Indication. This bit goes high when the SE counter is incremented (i.e., when the LSB of the SE counter toggles). It goes low when bit 7 (SER) of the PMAC Control Word (Table 14, CSTi1 channel 11) is changed from high to low. It can also be cleared by a low on the INTA bit of the PMAC Control Word and will remain clear as long as the INTA bit is low. Framing Error Counter Saturation Indication. This bit is set when the FE counter overflows its terminal count (i.e., 1111 to 0000). It will be reset low when bit 6 (FER) of the PMAC Control Word (Table 14, CSTi1 channel 11) is changed from high to low. CRC Error Counter Saturation Indication. This bit is set when the CRC counter overflows its terminal count (i.e., 11111111 to 00000000). It will be reset when bit 5 (CRCR) of the PMAC Control Word (Table 14, CSTi1 channel 11) is changed from high to low. Valid for ESF only. Bipolar Violation Counter Saturation Indication. This bit is set when the BPV counter overflows its terminal count (11111111 to 00000000). It will be reset when bit 4 (BPVR) of the PMAC Control Word (Table 14, CSTi1 channel 11) is changed from high to low. Alarm Indication Signal. This bit is set when the MT8976/77 has lost synchronization and less than three zeros are detected in any 250 microsecond interval. It is reset when three or more zeros are detected in a 250 microsecond interval or when synchronization is regained. Table 11. Master Status Word 2 (CSTo Channel 31) 11111111. When the BPV counter wraps around the BPV Saturation Indication bit (BSI) will be set, Table 11, and a G2 interrupt will be asserted. Similarly, when the CRC counter wraps around the CRC Saturation Indication bit (CSI) will be set and a G2 interrupt will be asserted. The BPV and CRC counters, as well as the BSI and CSI bits, are cleared by a high-to-low transition of bit 4, BPV Counter Reset (BPVR), and bit 5, CRC Counter Reset (CRCR), of the PMAC Control Word channel 11 CSTi1, Table 14.
4
3
FSI
2
CSI
1
BSI
0
AIS
4-13
MT8926
Bit 7-0 Name RxBOM Description Received Bit-Oriented Message. This register contains the eight least significant bits of the ESF bit oriented message codeword. The contents of this register is valid when a bit-oriented message codeword is received by the MT8926 in the facility data link bit positions of consecutive extended superframes. A valid codeword will have the form 111111110XXXXXX0. The most significant eight bits (FF sequence) are received first. The register will contain the eight bits following the 11111111 sequence, which are 0XXXXXX0. When a valid codeword is detected, bit zero of the PMAC Miscellaneous Status Register is set. Table 12. Receive Bit-Oriented Message Register (CSTo Channel 27) Bit 7-0 Name TxBOM Description Transmit Bit-Oriented Message. The contents of this register will be appended to an FF flag to form a bit-oriented codeword, and clocked out on FDLo when bit zero in the PMAC Control Word is set high. The MT8926 will continue to clock this message out until bit 0 in the Control word is reset. The order of transmission is Bit 7 first. Bits 7 and 0 should be zero for a code word to be valid. Table 13. Transmit Bit-Oriented Message Register (CSTi1 Channel 7) Alarm Indication Signal (AIS) An AIS or Blue alarm is an all ones signal that can be transmitted from the network side to the terminal equipment side of an interface or from the terminal equipment side to the network side of an interface. In the first case, it indicates that the T1 signal from the network may be lost, and the timing that the terminal equipment derives from the received AIS may not be from the network. In the second case, it indicates that data from the terminal equipment side of an interface has been lost and AIS is being transmitted in its place. The MT8926 will detect an AIS alarm and indicate its presence by making the AIS bit of Master Status Word 2 (Table 11, CSTo channel 31 bit 0) high. This state occurs when the MT8976/77 has lost synchronization and less than three zeros are detected in any 250 microsecond interval. The AIS bit will go low when either of these conditions is no longer true. MT8926 FDL Message Transfer The MT8926 will support the transfer of FDL bitoriented messages in a format that is consistent with T1.403 and T1.408. A BOM is transmitted by loading the message into the PMAC Transmit Bit-Oriented Message Register (TxBOM), Table 13, CSTi1 Channel 7. This data has the form 0XXXXXX0, where XXXXXX is the content of the T1.403/408 message. When FDLEn (bit zero of the PMAC
4-14
Control Word, Table 14) is made high, the BOM is transmitted on the FDL preceded by 11111111. The start of the bit-oriented message is not synchronous with FDLEn going high. Therefore, to ensure a message is sent a minimum of n times, the message must be transmitted for 32n + 32 ST-BUS frames. Valid codewords that are received on the FDL are loaded into the Receive Bit-Oriented Message Register (RxBOM, see Table 12). A codeword is valid if it fits the 11111111 0XXXXXX0 form, however, only the 0XXXXXX0 portion of the message will appear in the RxBOM register. When a valid codeword has been received the BOMV bit of the PMAC Miscellaneous Status Word (Table 5, CSTo channel 7 bit 0) will be high. If the next received codeword is not valid, the BOMV bit will become zero and the RxBOM register will retain its most recent valid message. The MT8926 will support LAPD message-oriented performance reporting when it is combined with an HDLC controller such as the MT8952. See Figure 7 for FDL operation. The performance monitoring data that makes up the LAPD message is derived by the combination of MT8976/77 T1 framer and MT8926 PMAC, and is available on CSTo. This data can then be assembled into a LAPD message and presented to the MT8952 HDLC controller for transmission over the FDL on a one second basis as per T1.403/408 (see Figure 10). FDLEn of the PMAC Control Word (CSTi1 channel 11 bit 0) must be low to allow transmission of a performance report from the HDLC controller through pins FDLi and FDLo of the
MT8926
Bit 7 Name SER Description SE Counter Reset. Toggling this bit from high to low will reset the severely errored framing event counter (SE counter, CSTo channel 19 bits 7-4) and event indicator (SEI bit, CSTo channel 31 bit 4). FE Counter Reset. Toggling this bit from high to low will reset the framing error counter (FE counter, CSTo channel 19 bits 3-0) and saturation indicator (FEI bit, CSTo channel 31 bit 3). CRC Counter Reset. Toggling this bit from high to low will reset the eight bit CRC error counter (CRC, CSTo channel 11) and saturation indicator (CSI bit, CSTo channel 31 bit 2) BPV Counter Reset. Toggling this bit from high to low will reset the eight bit BPV counter (BPV, CSTo channel 23) and saturation indicator (BSI bit, CSTo channel 31 bit 1). Framing Pattern Select. With FSel = 1 and an SF signal detected, both FS and FT errors are considered by the FE and SE counters. The user must set this bit high in ESF mode. With FSel = 0 and an SF signal detected, only errors in FT bits are considered by the FE and SE counters. 2 8KEn 8 KHz Output Enabled. When 8KEn = 1, the E8Ko output will be enabled. That is, the signal input at E8Ki will be output on E8Ko. See Figure 12 for timing. When 8KEn = 0, the E8Ko output will be high. 1 INTA Interrupt Acknowledge. When INTA = 1 the MT8926 interrupts are armed or have been triggered (see Table 15). Once INTA is set all interrupting signals of a group must be inactive before another interrupt of that group can assert the IRQ output (active low). See Pin Description, pin 20. When this bit is low the IRQ output state will be high impedance. IRQ will remain in this state as long as INTA remains low or there are no interrupting events (Tables 16 and 17). 0 FDLEn Facility Data Link Enable. FDLEn = 1 enables transmission of the facility data link bitoriented messages on FDLo. The BOM byte is stored in the TxBOM register (Table 13, CSTi1 Channel 7). See Figure 7 for illustration. When FDLEn = 0, the data received on FDLi is multiplexed back out of the MT8926 on FDLo. See Figure 19 for timing. Table 14. PMAC Control Word (CSTi1 Channel 11) MT8926 to the TxFDL input of the MT8976/77. The 1SEC output pin or the two second TMR bit of the Miscellaneous Status Word (CSTo channel 7 bit 0) are derived from the ST-BUS timing and can be used to initiate the transmission of these messages. When the MT8926 is synchronized to an SF T1 signal, its receive FDL functions are disabled. BOMV of the PMAC Miscellaneous Status Register and RAI of Master Status Word 1 will be zero.
6
FER
5
CRCR
4
BPVR
3
FSel
4-15
MT8926
To System { Control CSTo 1SEC MT8926 CSTi1 To PMAC Control TxBOM 0XXXXXX 0 11111 11 1 From System Control MT8976/77 CSTi1 TxA RxA RxB ECLK
MT8952 CDSTo
2 TO 1 MUX FDLi FDLo
TxFDL TxB TxFDLCLK RxFDL RxFDLCLK
CDSTi FDLEn CKi
System Control
PCW FDLEn = 1 - Transmission of a Bit-oriented Message over the FDL. PCW FDLEn = 0 - Transmission of an MT8952 (HDLC Controller) assembled message-oriented signal over the FDL.
Figure 7 - T1.403/408 FDL Message Transmission 8 kHz Control Figure 9 illustrates a typical MT8976/77 - MT8926 application. This diagram shows E8Ko (an 8 kHz output aligned with the received framing bit) of the T1 framer connected to E8Ki of the PMAC. The PMAC uses this signal for frame alignment, therefore, the 8kHSel (Master Control Word 1) of the MT8976/77 must be active for the framer - PMAC combination to function properly, even if the interface is in master mode. See the MT8976/77 data sheet.
INTA
V DD
D
SEI* FSI CSI BSI INTERRUPT SOURCES From Snap-shot registers Group 1 Group 2
Q
IRQ
D
Q
R D
VDD
Q
R D Q
RAI ALRM MT8976/77 SYN MT8976/77 SLIP
D
Q
R
Toggle Detector R
Delayed Frame Pulse**
Delay * SEI is reset to 0 when INTA = 0. ** Delayed Frame Pulse occurs during Bit 7 of ST-BUS Channel 1.
Figure 8. Functional Schematic of Interrupt Mechanism
4-16
MT8926
In slave or loop-timed operation 8KEn of the PMAC Control Word (Table 14, CSTi1 channel 11 bit 2) will be high, which will pass the signal on E8Ki through to E8Ko. In Master mode or if loop-timing is acquired from another interface, 8KEn must be low, which will make E8Ko high. Interrupts The MT8926 interrupts originate from eight sources, which are divided into two groups. Group one (G1) contains ALRM (SF Yellow Alarm), RAI (ESF Yellow Alarm), SLIP and SYN - all except SLIP must be cleared by some means external to the MT8926. Group two (G2) contains SEI, FSI, CSI, and BSI these can be cleared via the MT8926. See Tables 16 and 17 for further information. The interrupting mechanism is controlled by the interrupt acknowledge bit (INTA) of the PMAC control word (Table 14). The status of the interrupts is output on IRQ. This will allow the three valid states described in Table 15.
.
When a G1 interrupt occurs and IRQ goes low (Triggered), no other G1 or G2 interrupts will affect IRQ. If IRQ is then Cleared and re-Armed, only an active G2 interrupt can Trigger IRQ low unless the G1 interrupt has been removed. That is, both the MT8926 interrupt mechanism and the interrupting source of a group must be cleared before a further interrupt of that group can cause IRQ to go low. The only exception to this is SEI, which can be cleared by INTA ( see Table 11). A PMAC interrupting signal is either a low-to-high transition or a change in state (SLIP), therefore, for IRQ to go low the MT8926 must be Armed before the initiating edge occurs. In the case where all interrupts are quiescent and then an interrupt becomes active, while the MT8926 is in its Clear state, IRQ will remain in a high impedance condition. This is true even if the MT8926 is then put in the Armed state and the interrupt persists (see Figure 8). It should be noted that when an SF mode T1 signal is being received the MT8926 CRC error counter will be incremented once every two superframes (24 frames or 3 msec.). This is because SF mode T1 has no CRC bits. Therefore, the CRC circuitry of the MT8976/77 will compare the calculated CRC remainder with the received FS bits, which will result in a mismatch. This will increment the MT8976/77 and MT8926 CRC error counters. The MT8926 CRC error counter will count to 255 and then overflow to zero, which will cause an interrupt (IRQ). Therefore, when an SF mode T1 signal is being received an interrupt will be asserted every 256 X 3 msec. = 768 msec. This can be avoided by clearing the CRC error counter before it overflows. A change of state of the 1SEC output (once every 0.5 seconds) can be used to trigger a high-to-low
State
INTA Bit
IRQ Output
Cleared 0 High Impedance Armed 1 High Impedance Triggered 1 0 Table 15. Interrupt States In the Cleared state (INTA = 0) interrupt sources are ignored and IRQ will always be high impedance. If the interrupts are not being used, then INTA should remain in the Cleared state. When the MT8926 is in the Armed state and an interrupt occurs, it will go to the Triggered state (IRQ = 0).
Signal ALRM RAI SLIP
To Trigger interrupt (IRQ low) ALRM bit low to high AND other G1 interrupts quiescent AND IRQ high impedance. RAI bit low to high AND other G1 interrupts quiescent and IRQ high impedance. CSTi0/CSTo Channel 15 Bit 1 (SLIP) changes state AND other G1 interrupts quiescent AND IRQ high impedance. CSTi0/CSTo Channel 15 Bit 0 (SYN) low to high AND other G1 interrupts inactive AND IRQ high impedance.
To Clear and Arm interrupt (IRQ high impedance) The INTA bit of the PMAC Control Word (CSTi1 channel 11 bit 1) should be made low to clear the interrupt mechanism (IRQ high impedance). All G1 interrupts must be quiescent and then INTA must be made high before a further interrupt can be generated from G1. See MT8976/77 data sheet master status word 1 for information on the SLIP and SYN bits.
SYN
G1 interrupts are cleared when SYN, ALRM, and RAI = 0. The SYN interrupt indicates that a LOS or a AIS condition may exist. Note: AND denotes a logical and.
Table 16. Group One (G1) Interrupt Activation and Clearing
4-17
MT8926
transition of the CRCR bit (CSTi1 channel 11 bit 5, PMAC Control Word). This will ensure the CRC error counter never overflows. SLIP and SYN Interrupts The MT8976 SLIP and SYN status bits are passed to the PMAC via the MT8976/77 CSTo to PMAC CSTi0 connection. A MT8926 interrupt will be initiated when the SLIP bit of the framer changes state. This is the only interrupt source that does not have to be cleared before another interrupt of that group can make IRQ go low. Therefore, when IRQ is returned to a high impedance condition after a SLIP interrupt and all other G1 interrupts are quiescent, any G1 interrupt can make IRQ to go low. A Low-to-High transition of the MT8976/77 SYN bit will initiate a PMAC interrupt. This loss of synchronization situation may indicate that a loss of signal condition (LOS) exists or that an all ones (AIS or Blue Alarm) is being received. Therefore, the SYN interrupt service routine should check the state of the AIS and LOS bits of CSTo.
Signal SEI
To Trigger interrupt (IRQ low) SEI bit low to high AND other G2 interrupts quiescent AND IRQ high impedance. FSI bit low to high AND other G2 interrupts quiescent AND IRQ high impedance. CSI bit low to high AND other G2 interrupts quiescent AND IRQ high impedance. BSI bit low to high AND other G2 interrupts quiescent AND IRQ high impedance.
To Clear and Arm interrupt (IRQ high impedance) The INTA bit of the PMAC Control Word (CSTi1 channel 11 bit 1) should be made low to clear the interrupt mechanism (IRQ high impedance). All G2 interrupts must be clear and INTA must be high before a further interrupt can be generated from G2. The SEI bit will remain clear as long as the INTA bit is low. SEI can also be cleared (low) by toggling SER (CSTi1 channel 11 bit 7) from high to low. FSI is cleared (low) by toggling FER (CSTi1 channel 11 bit 6) from high to low. CSI is cleared (low) by toggling CRCR (CSTi1 channel 11 bit 5) from high to low. Valid for ESF only. BSI is cleared (low) by toggling BPVR (CSTi1 channel 11 bit 4) from high to low.
FSI
CSI
BSI
G2 interrupts are cleared when SEI, FSI, CSI and BSI = 0. Note: AND denotes a logical and.
Table 17. Group Two (G2) Interrupt Activation and Clearing
4-18
MT8926
Applications
Figure 9 illustrates a typical application of a MT8926 PMAC. T1 data is transmitted and received using a generic Line Interface Unit (LIU). The LIU passes the received data and extracted clock to both the MT8926 and MT8976. E8Ko (MT8976) is derived from E1.5i by dividing it by 193 and aligning the result with the receive framing. E8Ko (MT8976) connects to E8Ki (MT8926), and is used by the MT8926 for frame alignment. E8Ko (MT8926) is connected to C8Kb of the MT8941. In MT8941 normal mode, C8Kb is the reference clock for the STBUS and transmit signals (F0, C4 and C2). This 8 kHz output can be turned off (output high) at the MT8926 so the MT8941 reference clock can be derived from another interface. The intrinsic jitter (typical 0.07 UI) and jitter attenuation of the MT8941 will meet T1.408 requirements (see MT8941 data sheet). Control of the MT8926 is accomplished over the CSTi1 ST-BUS stream, which is shared by the MT8926 and MT8976. Status data (Performance Monitoring Information) is inserted into the MT8976 CSTo stream by the MT8926 and is output on its CSTo stream. This CSTo stream data is routed through the MT8980 switch, in message mode, to the microprocessor. The microprocessor will assemble the information section of the T1.403/T1.408 message-oriented signal and pass it to the MT8952 HDLC controller for transmission over the facility data link. The MT8952 must be in external timing mode and will be clocked by the RxFDLCLK output to the MT8976. The assembly and transmission of the message-oriented signal is under control of the 1SEC output of the MT8926. Bit-oriented messages are also transmitted and received via MT8980 message mode access to the CSTi1 and CSTo streams. The MT8926 will receive bit-oriented messages from the receive T1 line (i.e., RxA and RxB). Both bit-oriented and messageoriented signals are transmitted over the MT8926 FDLo to MT8976 TxFDL link. Payload loopback is performed by internally connecting DSTi1 to DSTo of the MT8926 (under control of the CSTi1 stream), instead of the normal connection of DSTi0 to DSTo (see Figure 6). IRQ is an open drain interrupt output that will signal the microprocessor when an exception condition occurs (see Figure 8). Exception conditions are
C8Kb
From other interfaces
* *
16.384 MHz Osc.
MT8941
C4b C2o F0b F0i CVb
12.352 MHz Osc. To other T1 Interfaces
MT8980 To/From other interfaces * * *
STi2 STo3
* * *
C4i F0i
} To other Interfaces
Line Interface Unit (LIU)
T1 Receive
STo0 STo1 STo7 STi0 STi7 STo2 STi1
MT8926
E8Ko CSTo DSTi0 DSTi1 RxA RxB ECLK F0i C2i CSTi1 E8Ki CSTi0 FDLo DSTo
MT8976
C1.5i RxA TxA TxB RxB E1 5i F0i C2i CSTi1 E8Ko CSTo TxFDL RxSF DSTi TxSF DSTo XCtl CSTi0 RxFDL RxFDLCLK TxFDLCLK
A AAAAAAAAAAAAAAAAAAA A VDD A A A A A A P A Performance A 4.7k A A A A Monitoring A A INT0 A A Message/ A A INT1 A A Data A A A A Storage A A A AAAAAAAAAAAAAAAAAAAAA A AA A A AA A AA A AA MT8952 A AA A AA A AA A AA A CDSTo AA A AA A AA A AA A CDSTi AA A AA A AA A AA T1.403/T1.408 A CKi AA A Message-Oriented AA A AA A AA Signal Control A AA A AA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA AAAA A AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AA A AAAA A AA A
T1 Transmit
IRQ 1SEC FDLi
Figure 9 - Typical T1.403/T1.408 Application
4-19
MT8926
counter overflows and alarms. Interrupts are reset via the PMAC Control Word of the CSTi1 control stream. T1.403/408 FDL Message Transfer Overview ANSI standards T1.403 and T1.408 define an ESF mode Facility Data Link (FDL), which is used to transport performance information and control signals across a T1 link. The FDL channel is formed from the framing bit position of every second frame, and therefore, has a 4 KBit/sec. bandwidth. See Table 18 for the ESF Framing Pattern. FRAME # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 FPS FDL X CB1 X 0 X CB2 X 0 X CB3 X 1 X CB4 X 0 X CB5 X 1 X CB6 X 1 Table 18. ESF Frame Pattern The following two FDL message formats are defined in T1.403/408: 1) Bit-oriented, which are repeated 16 bit patterns or codeword messages, and Message-oriented performance reports, which are LAPD protocol messages. When data for the next one second interval t0+1 is gathered, it will take the place of t0 data of the last message. The t0 data will move to the t 0-1 position, the t0-1 data will move to the t0-2 position, the t0-2 data will move to the t0-3 position, and the data of t03 will be discarded. Refer to T1.403 or T1.408 for a more complete definition of this protocol. User defined Operations, Administration and Maintenance (OA&M), terminal-to-network and terminal-to-terminal communications may also pass over the FDL. Each message consists of a 16 bit codeword of the form 11111111 0XXXXXX0, which is repeated at least 10 times. The LAPD message-oriented performance reports are sent across the FDL once per second using the bit-assigned message structure of Figure 10. Each report contains performance data for each second of the previous four seconds. 5) unassigned. 4) reserved for network use, and 3) synchronization control, 2) protection switch control, 1) line and payload loopback control, Command and response messages are used to perform various functions, which include the following: CRC message consists of a 16 bit codeword of the form 11111111 0XXXXXX0. Therefore, there are 64 unique codewords or messages defined by XXXXXX. Refer to T1.403 or T1.408 for a list of messages and message restrictions. BOMs are further divided into priority messages, and command and response messages. Priority messages indicate the existence of a serviceaffecting failure, and are repeated until the condition that caused the message is removed. These BOMs are transmitted for at least one second, but may be interrupted as often as once per second, for a maximum of 100 msec. This is to accommodate the periodic transmission of message-oriented performance reports.
2)
Bit-oriented messages (BOMs) are preemptive, and therefore, override other FDL communications. Each
4-20
MT8926
OCTET # 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 7 6
OCTET LABEL 5 4 3 2 1
OCTET CONTENT
FLAG SAPI TEI CONTROL G3 FE G3 FE G3 FE G3 FE LV SE LV SE LV SE LV SE G4 LB G4 LB G4 LB G4 LB U1 G1 U1 G1 U1 G1 U1 G1 FCS U2 R U2 R U2 R U2 R G5 G2 G5 G2 G5 G2 G5 G2 SL Nm SL Nm SL Nm SL Nm G6 NI G6 NI G6 NI G6 NI C/R EA EA
01111110 00111000 or 00111010 00000001 00000011
} } } }
to
to-1
ONE-SECOND REPORT
to-2
to-3
ADDRESS 00111000 00111010 00000001 CONTROL 00000011 ONE-SECOND REPORT G1 = 1 G2 = 1 G3 = 1 G4 = 1 G5 = 1 G6 = 1 SE = 1 FE = 1 LV = 1 SL = 1 LB = 1 U1, U2 = 0 R=0 NmNI = 00, 01, 10, 11 FCS Variable
INTERPRETATION SAPI = 14, C/R = 0 (CI) EA = 0 SAPI = 14 C/R = 1 (Carrier) EA = 0 TEI = 0, EA = 1 INTERPRETATION Unacknowledged Information Transfer INTERPRETATION CRC Error Event = 1 1Figure 10 - Message-Oriented Performance Report Structure (from T1.403 and T1.408)
4-21
MT8926
Absolute Maximum Ratings*
Parameter 1 2 3 4 Power Supplies with respect to VSS Voltage on any pin other than supplies Current at any pin other than supplies Storage Temperature TST -40 Symbol VDD Min -0.3 VSS-0.3 Max 7 VDD+0.3 40 125 500 Units V V mA
C
5 Continuous Power Dissipation PD * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
mW
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics 1 2 3 Operating Temperature Power Supplies Input High Voltage Sym TOP VDD VIH Min -40 4.5 2.4 5.0 Typ Max 85 5.5 VDD Units C V V Noise margin = 150 mV margin = 400 mV Test Conditions
4 Input Low Voltage VIL VSS 0.4 V Noise Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics - Clocked operation over recommended temperature ranges and power supply voltages.
Parameters 1 2 3 4 5 6 Supply Current Input High Voltage Input Low Voltage Input Leakage Current Output High Current Output Low Current
Sym IDD VIH VIL IIL IOH IOL
Min
Typ
Max 5
Units mA V V A mA mA
Test Conditions Outputs Unloaded
2.25 VSS
VDD 0.8 10
Digital Inputs VIN=0 to VDD VOH=2.4V VOL=0.4V
.
8 8
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics - Capacitance
Parameters 1 2 Input Pin Capacitance Output Pin Capacitance Sym CI CO Min Typ 10 10 Max Units pF pF Test Conditions
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. Timing is over recommended temperature ranges and power supply voltages.
AC Electrical Characteristics - DS1 Link Timing (Figure 11)
Parameters 1 2 3 4 Receive Data Setup Time Receive Data Hold Time Extracted Clock Width Extracted 1.5 MHz Clock Period Sym tRS tRH tECW tP1.5 Min 0 30 250 500 324 649 Typ Max Units ns ns ns ns Test Conditions
Timing is over recommended temperature & power supply voltage ranges. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
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MT8926
Received T1 Link Bit Cells tRS 2.25V RxA, RxB 0.8V
BIT CELL tRM
tECW 2.25V ECLK 0.8V
tECW
tP1.5
Figure 11 - Receive T1 Link Timing
AC Electrical Characteristics - 8 kHz Timing (Figures 12)
Parameters 1 2 3 4 8kHz Propogation Delay 8kHz Setup Time 8kHz Input Low 8kHz Input High Sym t8PD t8S t8IL t8IH 45 0.065 78 47 Min Typ Max 20 Units ns ns s s Test Conditions 50 pF load
Timing is over recommended temperature & power supply voltage ranges. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
DATA
Channel 2 Bit 1
***
Channel 17 Bit 2
***
Channel 2 Bit 1
ECLK
2.25V 0.8V t8S 2.25V t8S
E8Ki
0.8V t8IL t8IH
E8Ko
2.4 V 0.4 V t8PD t8PD
Figure 12 - 8kHz Extracted Framing Signal
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MT8926
AC Electrical Characteristics - 2048 kBit/s ST-BUS Streams (Figures 13 and 14)
Parameters 1 2 3 4 Clock to Output Delay ST-BUS Setup Time ST-BUS Hold Time Serial Output Delay
y
Sym tCOD tSTS tSTH tSOD
Min
Typ
Max 125
Units ns ns ns
Test Conditions 150 pF load
15 50 35 15 40
ns
150 pF load CSTo 50 pF load CSTo 150 pF load DSTo
Timing is over recommended temperature & power supply voltage ranges. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing. Note - The PMAC is overwriting some of the bits received on CSTi0, and transmitting the aggregate on CSTo. Line loopback codes are being transmitted on DSTo. Notey - The ST-BUS stream being received on CSTi0 is not being overwritten, but passes through the PMAC unaltered. DSTi0 and DSTi1 are not overwritten, but passes through the PMAC unaltered to the DSTo output.
BIT CELL BOUNDARIES 2.25V C2i 0.8V tCOD 2.4V CSTo, DSTo 0.4V tCOD
CSTi0/1
2.25V 0.8V tSTS tSTH
Figure 13 - ST-BUS Timing - CSTo/DSTo Altered by PMAC
DSTi0/1, CSTi0
2.25V 0.8V tSOD 2.4V
DSTo, CSTo
0.4V
Figure 14 - ST-BUS Timing - CSTo/DSTo Unaltered by PMAC
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MT8926
AC Electrical Characteristics - Clock and Frame Pulse Timing (Figure 15)
Parameters 1 2 3 4 C2i Clock Period C2i Clock Width High or Low Frame Pulse Setup Time Frame Pulse Width High Sym t2P t2W tFPS tFPH Min 400 200 50 50 Typ 488 244 Max 600 300 Units ns ns ns ns Test Conditions
5 Frame Pulse Width Low tFPL 50 ns Timing is over recommended temperature & power supply voltage ranges. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
t2P 2.25V C2i 0.8V t2W tFPS 2.25V F0i 0.8V tFPH tFPL t2W
Figure 15 - ST-BUS Clock and Frame Pulse Timing
AC Electrical Characteristics - 1SEC Output Timing (Figure 16)
Parameters Sym Min Typ Max Units Test Conditions pF load 1 1SEC Output Delay t1SD 95 ns 150 Timing is over recommended temperature & power supply voltage ranges. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
F0i C2i
2.25V 0.8V 2.25V 0.8V 2.4V 0.4V
1SEC
t1SD
t1SD
Figure 16 - 1SEC Timing
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MT8926
Frame n Ch 0 CSTi0/1 ** 1 0 7 Frame n + 1 Ch 1 6 2 Ch 11 1* 0 7 Ch 12 6
C2i
t IOD IRQ * ** Note: High Z
tIOD
High Z Active Low INTA Bit. IRQ is returned to High Z by INTA=0, INTA=1 in the previous frames. This can occur in frame n+1 or in a later frame. Condition initiating interrupt tIOD (IRQ Output Delay) is dependent on the IRQ pull-up resistor.
Figure 17 - Interrupt Functional Timing
AC Electrical Characteristics - Facility Data Link Timing (Figures 18 and 19)
Parameters 1 Data Link Output Delay Sym tDOD Min Typ Max 45 Units ns Test Conditions 150 pF load 150 pF load
2 Data Link Propagation Delay tDPD 40 ns Timing is over recommended temperature & power supply voltage ranges. Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
Ch 11 1 C2i * 7
Ch 12 6 2
Ch 31 1 0 7 6 5
Ch 0 4
F0i tDOD FDLo 2.4V 0.4V FDLi Data *FDLEn = 1, FDLEn=0 in the previous frames. TxBOM Data
Figure 18 - FDL Bit-oriented Message Timing
FDLi
2.25V AA 0.8V AA tDPD 2.4V AA 0.4V AA
AAA AAA A AA AA AA
FDLo
Note: FDLEn = 0
Figure 19 - FDL Message-oriented Signal Timing
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MT8926
Appendix
Control and Status Register Summary 7
Debounce 1 Disabled 0 Enabled
6
TSPZCS 1 Disabled 0 Enabled
5
B8ZS 1 B8ZS 0 Jammed Bit
4
8KHSel 1 Disabled 0 Enabled
3
XCtI 1 Set High 0 Cleared
2
ESFYLW 1 Enabled 0 Disabled
1
Robbed Bit 1 Disabled 0 Enabled
0
YLALR 1 Enabled 0 Disabled
Master Control Word 1 (Channel 15, CSTi0)
RMLOOP 1 Enabled 0 Disabled DGLOOP 1 Enabled 0 Disabled ALL 1's 1 Enabled 0 Disabled ESF/D4 1 ESF 0 D3/D4 Reframe Device Reframes on High to Low Transition SLC-96 1 Enabled 0 Disabled CRC/MIMIC See Note 1 Maint. 1 4/12 0 2/4
Master Control Word 2 (Channel 31, CSTi0)
Polarity UNUSED - KEEP AT 0 1 No Inversion 0 Inversion Loop 1 Ch. looped back 0 Normal Data 1 Enabled 0 Disabled
Per Channel Control Words (All Channels on CSTi0 Except Channels 3, 7, 11, 15, 19, 23, 27 and 31)
Transmitted First
TxBOM
Transmitted Last
Transmit Bit-Oriented Message Register (Channel 7, CSTi1)
SER High-to-Low Reset FER High-to-Low Reset CRCR High-to-Low Reset BPVR High-to-Low Reset 0 FT only 0 Disabled 0 Disabled/ Clear FSel 1 FS, FT, FPS 8KEn 1 Enabled INTA 1 Enabled FDLEn 1 TxBOM-toFDL 0 FDLi-to-FDLo
PMAC Control Word (Channel 11, CSTi1)
00 Normal UNUSED 01 Payload 10 LL Enable 11 LL Disable
Loopback Control Word (Channel 15, CSTi1)
UNUSED - KEEP AT 0
A Txt. Sig. Bit
B Txt. Sig. Bit
C Txt. Sig. Bit
D Txt. Sig. Bit
Per Channel Control Words (All Channels on CSTi1 Except Channels 3, 7, 11, 15, 19, 23, 27 and 31)
CHANNEL COUNT
BIT COUNT
Phase Status Word (Channel 3, CSTo)
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MT8926
Appendix (continued)
Control and Status Register Summary 7 6 5 4
LLDD 1 Detected UNUSED 0 Not Detected 0 Not Detected 0 Out-of-Sync
3
LLED 1 Detected
2
FECV 1 In-Sync
1
TMR Changes State once per second
0
BOMV 1 Valid 0 Invalid
PMAC Miscellaneous Status Word (Channel 7, CSTo)
CRC ERROR COUNT
Cyclic Redundancy Check-6 Error Counter (Channel 11, CSTo)
YLALR 1 Detected 0 Normal MIMIC 1 Detected 0 Not Detected ALRM 1 Detected 0 Not Detected RAI 1 Detected 0 Not Detected MFSYNC 1 Not Detected 0 Detected LOS 1 Detected 0 Normal SLIP Changes State when Slip Performed SYN 1 Out-of-Sync. 0 In-Sync
Master Status Word 1 (Channel 15, CSTo)
SEVERELY ERRORED FRAMING EVENT COUNTER (SE)
FRAMING ERROR COUNTER (FE)
Severely Errored Framing Event and Error Counters (Channel 19, CSTo)
BPV ERROR COUNT
Bipolar Violation Error Counter (Channel 23, CSTo)
Received First
RxBOM
Received Last
Receive Bit-Oriented Message Register (Channel 27, CSTo)
BlAlm 1 Detected 0 Not Detected FrCnt Frame Count XSt 1 XSt High 0 XSt Low SEI 1 SE Toggles 0 SER Highto-Low FSI 1 FE F-to-0 0 FEF Highto-Low CSI 1 CRC FFto-00 0 CRCR Highto-Low BSI 1 BPV FF-to00 0 BPVR Highto-Low AIS 1 Detected 0 Not Detected
Master Status Word 2 (Channel 31, CSTo)
UNUSED
A Rec'd. Sig. Bit
B Rec'd. Sig. Bit
C Rec'd. Sig. Bit
D Rec'd. Sig. Bit
Per Channel Status Word (All Channels on CSTo Except Channels 3, 7, 11, 15, 19, 23, 27, 31)
Note 1: In ESF mode: 1: CRC calc. ignored during Sync. 0: CRC checked for Sync. In D3/D4 mode: 1: Sync. to first correct S-bit pattern. 0: Will not Sync. if Mimic detected.
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